Lesson 3

The SR latch is somewhat impractical as a building block for memory, due to the separate inputs required for storing \(1\) or \(0\), and because of the “forbidden” input state \((0,0)\). The Data Latch extends this construction by introducing a more practical interface: a single input for the data and an additional input that indicates whether the data should be stored.

Problem. Synthesize a circuit of size \(4\) over \(\{\operatorname{SRLATCH}, \operatorname{NAND}_{2}, \operatorname{INV}_{1}, \operatorname{AND}_{2}, \operatorname{OR}_{2}, \operatorname{XOR}_{2}, \operatorname{SELECT}\}\) computing a D latch \(\operatorname{DLATCH}(st,d)\): The input-label line is \(\texttt{st d}\), and the circuit has a one-bit output. If \(\texttt{st}\)=1, store and output \(\texttt{d}\); if \(\texttt{st}\)=0, retain the previous output. The state is undefined until the first input with \(\texttt{st}\)=1.