Lesson 2

Problem. Synthesize a circuit of size \(2\) over \(\{\operatorname{NAND}_{2}, \operatorname{AND}_{2}, \operatorname{OR}_{2}, \operatorname{INV}_{1}, \operatorname{XOR}_{2}\}\) computing an SR latch \(\operatorname{SRLATCH}(s,r)\): The input-label line is \(\texttt{s r}\), and the circuit has a one-bit output. \[\begin{array}{c c | l} s & r & \text{output} \\ \hline 1 & 0 & 1 \\ 0 & 1 & 0 \\ 1 & 1 & \text{previous output} \\ 0 & 0 & \text{undefined}\end{array}\] The state is undefined initially and after any input \(\texttt{0 0}\), until the next set or reset. In this task, cycles in the circuit are allowed: a gate may use a label defined on a later gate line.