Lesson 4

Using latches, one can construct a circuit whose state evolves over time. However, a difficulty arises: since data changes are not synchronized throughout the circuit, changes propagate in an unpredictable manner, giving rise to race conditions and, more generally, to indeterminate behavior. The standard remedy is the introduction of a clock signal, that is, a one-bit signal that changes periodically and is connected to all stateful components. If components are permitted to modify their outputs only in response to changes in the clock signal, then state transitions occur simultaneously across the circuit, thereby eliminating synchronization issues. In this task, you are required to construct a flip-flop component that stores a bit while the clock signal is equal to \(1\), but begins emitting the stored bit only when the clock signal transitions to \(0\).

Problem. Synthesize a circuit of size \(4\) over \(\{\operatorname{DLATCH}, \operatorname{NAND}_{2}, \operatorname{INV}_{1}, \operatorname{AND}_{2}, \operatorname{OR}_{2}, \operatorname{XOR}_{2}, \operatorname{SELECT}\}\) computing a data flip-flop \(\operatorname{DFF}(st,d,cl)\): The input-label line is \(\texttt{st d cl}\), and the circuit has a one-bit output. Initially, the clock is set to zero. On a rising clock edge, store \(\texttt{d}\) if \(\texttt{st}\)=1; publish the stored value on the following falling edge; otherwise retain the previous value. Assume \(\texttt{st}\) and \(\texttt{d}\) do not change while \(\texttt{cl}\)=1. The output is undefined before the first completed store-and-clock cycle.