Lesson 1

A processor employs both types of memory, namely registers and RAM. Registers are directly accessible to the processor and are used to store intermediate values and computation results. In contrast, RAM is capable of storing a substantial amount of data; however, only a single address can be accessed for reading or writing at any given time. In the present processor architecture, two registers, denoted \(A\) and \(D\), are available in addition to a single RAM bank. In this task, you are required to integrate the two registers with the RAM bank into a unified memory system. Here the provided \(\texttt{RAM16}\) gate is a word-address adapter: it takes, in order, a one-bit store flag, a 16-bit data value, a 16-bit address, and a one-bit clock signal, and writes one 16-bit value. It selects between its two cells using the least significant bit of the address.

Problem. Synthesize a circuit of size \(3\) over \(\{\operatorname{REGISTER}_{16},\allowbreak \operatorname{RAM}_{16},\allowbreak \operatorname{NAND}_{2},\allowbreak \operatorname{INV}_{1},\allowbreak \operatorname{AND}_{2},\allowbreak \operatorname{OR}_{2},\allowbreak \operatorname{XOR}_{2}\}\) computing the combined-memory function \(\operatorname{MEMORY}_{16}(a,d,\texttt{*a},x,cl)=(A,D,\texttt{*A})\): Here \(x,A,D\), and \(\texttt{*A}\) are 16-bit values; \(a,d\), \(\texttt{*a}\), and \(cl\) are bits. The flags write \(\texttt{x}\) to register \(\texttt{A}\), register \(\texttt{D}\), and the two-cell RAM at address \(\texttt{A}\bmod 2\), respectively. A simultaneous write to \(\texttt{A}\) and \(\texttt{*A}\) uses the old value of \(\texttt{A}\) as the RAM address. Output \(\texttt{*A}\) is the currently addressed RAM value. All memory starts at \(0\).