Lesson 5

The gates \(\operatorname{ISNEG}(x)\) and \(\operatorname{ISZERO}(x)\) used below are the 16-bit extensions of the tests constructed earlier; each takes one 16-bit value and writes one bit.

Problem. Synthesize a circuit of size \(8\) over \(\{\operatorname{NAND}_{2}, \operatorname{INV}_{1}, \operatorname{AND}_{2}, \operatorname{OR}_{2}, \operatorname{XOR}_{2}, \operatorname{ISNEG}, \operatorname{ISZERO}\}\) computing the condition predicate: \(\operatorname{CONDITION}(\texttt{lt},\texttt{eq},\texttt{gt},x) = (\texttt{lt}\land [x < 0]) \lor (\texttt{eq}\land [x = 0]) \lor (\texttt{gt}\land [x > 0])\).

The input-label line is \(\texttt{lt eq gt}\); the predefined 16-bit label \(\texttt{x}\) is interpreted in two's-complement representation.