Lesson 3

The SR latch is somewhat impractical as a building block for memory, due to the separate input pins required for storing \(1\) or \(0\), and because of the “forbidden” input state \((0,0)\). The Data Latch extends this construction by introducing a more practical interface: a single input for the data and an additional input that indicates whether the data should be stored.

Problem. Construct a D latch (data latch). The two input bits are \(\texttt{st}\) and \(\texttt{d}\). The output of your circuit must be a single bit.

Your circuit will be tested on many sequences of input pairs \(\texttt{(st,d)}\). At each step, the output should behave as follows: \[\begin{array}{c c | l} st & d & \text{output} \\ \hline 1 & 0 & 0 \\ 1 & 1 & 1 \\ 0 & 0 & \text{previous output} \\ 0 & 1 & \text{previous output}\end{array}\] Thus, when \(\texttt{st}\)=1, the current value of \(\texttt{d}\) is stored and immediately output. When \(\texttt{st}\)=0, the last stored value is output and the current value of \(\texttt{d}\) is ignored. Until the first time \(\texttt{st}\)=1, the output is undefined, so any output is allowed.

You may use only the following functions: \[\begin{aligned}\operatorname{SRLATCH}(s,r) &= \text{the SR-latch output}, \\ \operatorname{NAND}(a,b) &= \neg(a \land b), \\ \operatorname{INV}(a) &= \neg a, \\ \operatorname{AND}(a,b) &= a \land b, \\ \operatorname{OR}(a,b) &= a \lor b, \\ \operatorname{XOR}(a,b) &= a \oplus b, \\ \operatorname{SELECT}(s,d_1,d_0) &= \begin{cases} d_0, & s=0, \\ d_1, & s=1. \end{cases}\end{aligned}\]

For example, a line \(\texttt{q s r SRLATCH}\) means that \(\texttt{q}\) is a new label equal to the current output of an SR latch with inputs \(\texttt{s}\) and \(\texttt{r}\).

The authors' solution uses \(4\) gates.